收藏本站
Chapter 3: Functional Description
Parameters
Table 3–15 shows the clocking options.
Table 3–15. Clocking Options
3–35
Parameter
Enable DQS mode
Use non-migratable DQ, DQS, and DM pins
Use fedback clock
Description
When turned on, the registers that capture data from the DQ pins during
reads are clocked by a delayed version of DQS. Otherwise, a PLL-
generated clock captures the data (Stratix series only).
DQS mode provides higher performance than non-DQS mode. (refer to
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices ).
Only top and bottom banks support DQS circuitry, but non-DQS mode
uses side banks too. (1)
Only Stratix II devices support this option.
When the option is turned off, there are pins that are common across
the devices in the same family. For example, the pins that are available in
EP2S130F1020C3 is also available in EP2S90F1020C3. If you compile a
DDR or DDR2 SDRAM design to an EP2S130F1020C3 device, later you
can easily migrate it to an EP2S90F1020C3 device.
When turned on, the wizard allows much greater flexibility in the
placement of DQ, DQS, and DM pins, but you lose the ability to migrate
the design to a migration device.
When turned on, the wizard uses the fedback clock for
resynchronization or capture. This clock eases resynchronization for the
read data for interface speeds > 200 MHz. When you use this clock, the
design uses an additional feedback PLL.
When you turn on both DQS mode and fedback clock mode, IP
Toolbench issues a warning Resynchronization and Postamble settings
must be chosen manually in the Manual Timings pane when using
DQS Fedback Clock mode . Manual control allows you flexibility to
adjust the phase of both the resynchronization clock and postamble
clock. If you do not turn on Manual control , the postamble clock and the
resynchronization clocks are derived from either the system clock or the
write clock.
For more information on fedback clock usage for improving the
performance, refer to Appendix D, Maximizing Performance . (1)
Note to Table 3–15 :
(1) For block diagram of the registers, refer to Figure A–2 and Figure A–4 on page A–6 .
? March 2009
Altera Corporation
DDR and DDR2 SDRAM Controller Compiler User Guide
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
IP-SLITE2 IP SERIALLITE II
IP-SRAM/QDRII IP QDRII SRAM CONTROLLER
IP-VITERBI/SS IP VITERBI LOW-SPEED
IP4220CZ6,125 IC USB DUAL ESD PROTECT 6TSOP
IPA-66-1-600-10.0-A-01-T CIRC BRKR 10A 2POLE SCREW TERM
IPR-CSC IP COLOR SPACE CONVERTER RENEW
IPR-ED8B10B IP 8B10B ENCODER/DECODER RENEW
IPS-VIDEO IP VIDEO/IMAGE PROCESSING SUITE
相关代理商/技术参数
IP-SDRAM/DDR3 功能描述:开发软件 DDR3 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/LPDDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPSE.4.33SM600 制造商:Banner Engineering 功能描述:FIBER IPSE.4.33SM600 GLASS FIBER (MIN ORDER 50)
IPSE.4.62SM600 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50)
IPS-EMBEDDED 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPS-EVAL-EH-01 功能描述:ENERGY HARVESTING BOARD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:THINERGY® 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP